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Revision 1.4
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AS5132
Datasheet - Detailed Description
7.3.6   Multi Turn Counter
A 9-bit register is used for counting the magnets revolutions. With each zero transition in any direction, the output of a special counter is
incremented or decremented. The initial value after reset is 0 LSB. Clockwise rotation gives increasing angle values and positive turn count.
Counter clockwise rotation exhibits decreasing angle values and a negative turn count respectively.
The counter output can be reset by using command 20  SET MT Counter. It is immediately reset by the rising clock edge of this bit. Any zero
crossing between the clock edge and the next counter readout changes the counter value.
7.3.7   High Speed Operation
The AS5132 is using a fast tracking ADC (TADC) to determine the angle of the magnet. The TADC is tracking the angle of the magnet with cycle
time of 2約 (typ. 1.4). Once the TADC is synchronized with the angle, it sets the LOCK bit in the status register. Once it is locked, it requires only
one cycle [2約 (typ. 1.4)] to track the moving magnet. The AS5132 can operate in locked mode at rotational speeds up to max.72,900 rpm.
7.3.8   Propagation Delay
The propagation delay is the time required from reading the magnetic field by the Hall sensors to calculating the angle and making it available on
the serial or PWM interface. While the propagation delay is usually negligible on low speeds, it is an important parameter at high speeds. The
longer the propagation delay, the larger becomes the angle error for a rotating magnet as the magnet is moving while the angle is calculated. The
position error increases linearly with speed.
7.3.9   Error Detection
The following errors are detected by the system:
n Lock bit ?/SPAN> the TADC has not yet found a valid angular position 
n AGC alarm ?/SPAN> the AGC value is 63, magnetic field is too weak
By default, Lock bit error should activate the error condition at the outputs. The AGC alarm is permanently available at the DIAG pin.
Error condition at commutation and incremental outputs:
n U, V and W outputs all 0
n A, B and I outputs all 1
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